The selective voltage binning (SVB) methodology provides a mechanism for reducing the maximum power on an chip by reducing the voltage on the parts that are faster than nominal, while running the slower than nominal parts at the full voltage. Post-manufacturing selective voltage binning is a technique that is used to sort manufactured chips into bins based on whether they were fabricated at either the “slow” end or the “fast” end of a process distribution and to vary the voltage requirements for the chips depending upon the bins they are assigned to in order to reduce maximum chip power. Specifically, with slower process chips it takes more voltage to turn on a transistor and less current is produced to drive the load. Thus, in the past the worst case process ranges drove the required voltage for ultimately running the chip. However, with selective voltage binning, every chip is tested to measure operating speed relative to a nominal speed, and the chips are sorted into bins accordingly. For example, in a process-voltage-temperature space, the temperature and voltage of the chip may be fixed and the operating speed of the chip may be measured. If the operating speed of a particular device is faster than a nominal speed, then the device is placed in a fast device voltage bin. If the operating speed is slower than the nominal speed, then the device is placed in a slow device voltage bin.
After the chips are sorted into bins, an optimal supply voltage (Vdd) for operating the chips in each bin is determined. Since both dynamic power consumption and static power consumption are exponentially proportional to the Vdd, a reduction in the required Vdd will reduce both dynamic and leakage power consumption and, thus, overall power consumption. When a particular chip is provided to a customer, it is provided along with information indicating one or both of its assigned voltage bin and the required supply voltage corresponding to its assigned voltage bin. For example, the assigned bin or supply voltage requirements may be recorded within or on a chip (e.g., by using a printed barcode or embedded non-volatile memory devices) for reference by a customer when setting up power supplies in a system using a particular chip.
Selective voltage binning is thus used for minimizing power consumption and optimizing voltage across the process space, while assuming a constant frequency throughout chip design and timing closure. However, many designs can run at faster frequencies depending on where they sit within the process space.